Seeking to keep Moore's Law on pace, researchers have developed a repeatable technique for assembling a single-atom version of the transistor--the building block of semiconductors and computers.
Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
As feature sizes continue to shrink at a breakneck pace, transistor-level analysis and optimization in digital design is becoming a necessity for achieving a solution with the unique combination of ...
Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual ...
This year, several companies are expected to bring 600/650 V Gallium Nitride (GaN) power transistors to market. Almost all will be normally-on (depletion mode) transistors connected in a cascode ...
Curious about how to precisely determine the optimal voltage-regulator setpoints for your System-on-Chip (SoC)? In this video, we dive into how transistor-level Power Delivery Network (PDN) telemetry ...
Determining the Fast-growing Risk of Soft Errors During Integrated Circuit Design Increases Reliability SANTA CLARA Calif. — October 6, 2004 — iRoC Technologies® Corporation introduced its SERPROâ ...
What is a Single-Electron Transistor? A single-electron transistor (SET) is a nanoscale electronic device that allows the precise control of individual electrons. Unlike conventional transistors that ...
(Nanowerk Spotlight) For years it has been known that scaling bulk silicon transistors would be extremely challenging, if not impossible, when lengths close in on 15 nm. Already, attention has turned ...
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