Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
EDN

Avery upgrades testbench automation products

ANDOVER, Mass. — Avery Design Systems Inc. said its upgrade of its SimLib testbench automation tools makes existing simulation environments more powerful. SimLib 2.0 includes new releases of ...
Electronic Design

Testbench Tool Exploits Distributed Compute Environments

Through an enhancement to inFact, Mentor Graphics’ intelligent testbench automation tool, large simulations can be automatically distributed across up to 1000 CPUs, extending non-redundant sequence ...
Machine Design

Test Bench Checks HVAC in Electric Vehicles

German researchers and an electromobility company create a test facility that mimics realistic driving conditions and includes a digital twin. Automakers need test-bench technology that is fast, ...