SAN FRANCISCO, Calif. — New IC devices, circuits, and physical effects will drive a new generation of timing analysis tools, said David Hathaway, senior technical staff member for EDA at IBM ...

A year or two ago, it looked like statistical timing analysis might be the next great new thing in IC design. Now it's less clear–and a debate at the recent International Symposium on Physical Design ...

Probabilistic timing analysis represents an emergent paradigm in the evaluation of real-time systems, addressing inherent uncertainties that traditional worst-case execution time (WCET) methods ...

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...

How to apply CAST-32A and A(M)C20-193 guidance for heterogeneous multicore processors. Techniques for measuring timing and interference on heterogeneous multicore processors. How to employ robust ...

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is ...

Software applications today control some of the most important functionalities in an automobile, ranging from basic safety functions like brake and airbag control, to driver assistance systems like ...

Graceful Shutdown: Ensuring the motor and controller are shut down safely when the application is stopped. If the application operates on a multicore MCU/DSP/FPGA, an appropriate inter-core ...