SAN FRANCISCO—SynaptiCAD released the first 64-bit Linux version of VeriLogger Extreme, a Verilog simulation and debug environment. According to SynaptiCAD (Blacksburg, Va.), the 64-bit simulator runs ...

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...

HENDERSON, Nev. — For most IC designers, logic simulation can never be fast enough. Aldec Corp. is paying attention, and is claiming that its new Riviera-Pro 2006.10 HDL simulator provides a 57 ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.

Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn’t received the attention and research it deserves, causing a ...